1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a device structure for reducing variations in threshold voltage Vth of a power semiconductor device having an MOS gate with time to stabilize electrical characteristics, and a method of fabricating the same.
2. Description of the Background Art
FIG. 19 is a fragmentary plan view of a power insulated gate bipolar transistor (referred to hereinafter as an IGBT) as an example of the conventional semiconductor devices. FIG. 20 is a cross-sectional view taken along the line XX—XX of FIG. 19.
In FIGS. 19 and 20, the reference numeral 1 designates a P+ substrate; 2 designates an N+ layer; 3 designates an N− layer; and 4 designates a semiconductor body comprised of the P+ substrate 1 the N+ layer 2 and the N− layer 3.
The reference numeral 5 designates a P+ base layer; 6 designates an N+ emitter layer; 7 designates a gate insulating film made of silicon oxide; 8 designates a gate electrode of polysilicon; 9 designates a gate interconnection line of Al; 10 designates an emitter electrode; 11 designates guard rings; 12 designates a passivation film for isolation between the gate electrode 8 and the emitter electrode 10; 13 designates an emitter wire bonding region; 14 designates a surface protective film of silicon nitride for covering the IGBT surface except the emitter wiring bonding region 13 and a gate bonding pad (not shown) which is a part of the gate interconnection line 8  9; 15 designates a channel stopper; 16 designates a silicon oxide film; 17 designates a polysilicon film; 18 designates a passivation film; and 19 designates a collector electrode.
FIG. 21 is a flow chart of the fabrication process of the conventional IGBT.
Referring to FIG. 21, the semiconductor body 4 is initially formed, and the P+ base layer 5, and P wells, P+ layers serving as the guard rings 11 are formed in the surface of the N− layer 3 of the semiconductor body 4. The gate insulating film 7 of silicon oxide is formed on the surface of the P+ base layer 5, and a polysilicon film is formed on the surface of the gate insulating film 7. Then the N+ emitter layer 6 and the channel stopper 15 are formed by diffusion, and the passivation films 12 and 17  18 are formed. The gate interconnection line 9 and the emitter electrode 10 are formed as Al electrodes. Thereafter, the surface protective film 14 is formed to cover the IGBT surface except the emitter wire bonding region 13 and the gate bonding pad which is a part of the gate interconnection line 9. A silicon nitride film serving as the surface protective film 14 is formed by plasma CVD process (referred to hereinafter as P-CVD process) at a temperature of about 300 to 400° C. in an atmosphere of a mixed silane-ammonia gas. Then the IGBT is exposed to radiation for lifetime control thereof and is subjected to heat treatment at a temperature of 300 to 400° C. to eliminate distortion resulting from the radiation.
The surface protective film 14 is formed for the following purposes: (1) to prevent shorting of the emitter electrode 10 and gate interconnection line due to mechanical scratches, (2) to prevent shorting of an aluminum electrode (not shown) formed on the guard rings 11 in a peripheral area of a chip due to external contamination, and (3) to prevent moisture from corroding aluminum thin wires of The device.
In the past, oxide films formed by the low pressure CVD process (referred to hereinafter as LP-CVD process), such as phospho-silicate glass (PSG), have been used as the surface protective film of the IGBT. However, silicon nitride films formed by the P-CVD process have recently been used as the surface protective film since the material of the silicon nitride films is more air-tight and mechanically stronger as a surface protective film than that of the PSG films. In this manner, the conventional IGBT is constructed as above described using the silicon nitride film formed by the P-CVD process as the surface protective film and is fabricated through the above-mentioned fabrication process.
To evaluate the long-term stability of electrical characteristics of the IGBT, a HTGB test (high temperature gate bias test) was performed. The HTGB test is to continuously apply a gate signal VGES≈+20 V or −20 V between the gate and emitter, with the emitter and collector grounded, at an atmospheric temperature Ta=125° C. to determine the relation between a VGES voltage application time and variations in threshold voltage Vth with time.
FIG. 22 is a graph of the result of the HTGB test made on the conventional semiconductor devices.
The test conditions in FIG. 22 are an atmospheric temperature Ta≈125° C. and VGES=±20 V for an IGBT, and an atmospheric temperature Ta=150° C. and VGES=−30 V for an MOSFET. Variations in threshold voltage Vth is represented by the percentage of Vth variations.
The MOSFET used herein is constructed such that the P+ substrate is removed from the structure of FIG. 20 and the N+ layer 2 is replaced with an N+ substrate. The fabrication process of the MOSFET does not include the radiation and the heat treatment for distortion elimination of FIG. 21.
Referring to FIG. 22, for the IGBT, with VGES=+20 V applied, the Vth variation percentage is several percent which presents no particular problems in terms of long-term stability of the electrical characteristics. For the IGBT, with VGES=−20 V applied, Vth decreases with the passage of the VGES application time, and the Vth variation percentage exceeds 10% after an elapse of 1000 hours. In addition, the Vth variation does not tend to become saturated over 1000 hours. Thus, the conventional IGBT has been disadvantageous in long-term stability of the electrical characteristics.
For the conventional MOSFET, with VGES=−30 V applied, Vth decreases with the passage of the VGES application time and tends to become saturated after an elapse of 500 hours, as compared with the IGBT. However, the MOSFET exhibits the Vth variation percentage reaching 10%. Thus, the conventional MOSFET has been disadvantageous in long-term stability of the electrical characteristics.
The application of a negative voltage VGES varies the threshold voltage Vth which in turn is slow in becoming saturated, possibly for the reasons to be described below.
The silicon nitride film formed by the P-CVD process contains a large amount of hydrogen atoms. For example, the number of Si—H chemical bonds in the silicon nitride film formed by the P-CVD process is 1.0×1022 cm—3 to 1.6×1022 cm−3 by measurement using FT-IR (Fourier transform infrared spectroscopy) technique. The number of Si—H chemical bonds in the PSG film is on the order of 0.4×1022 cm−3. The hydrogen atoms in the silicon nitride film readily migrate through the surface protective film 14 of silicon nitride, the aluminum electrodes such as the gate interconnection line 9 and emitter electrode 10, the passivation film 17  12 and the gate insulating film 7 of silicon oxide depending upon the atmospheric temperatures and the polarity and magnitude of the applied voltage to reach a silicon-silicon oxide interface at the surface of the semiconductor body 4 without difficulty. Dangling bonds at the silicon-silicon oxide interface are bonded to hydrogen atoms from the silicon nitride film to form Si—H chemical bonds at the silicon-silicon oxide interface, resulting in an unstable interface state. It takes time to stabilize the interface state, which is considered to cause the difficulty in saturating the varying threshold voltage Vth.
One of the reasons why such a problem is not encountered for the conventional PSG film is considered to be the fact that the PSG film contains fewer Si—H chemical bonds and, accordingly, fewer hydrogen atoms than the silicon nitride film formed by the P-CVD process.
Further, the radiation for lifetime control of the IGBT increases the defects at the silicon-silicon oxide interface to accelerate the formation of Si—H bonds at the silicon-silicon oxide interface, probably resulting in increased Vth variations with time.